During semiconductor device processing, metal interconnects can act as either anodes or cathodes of an electrolytic cell in the presence of a current source. In the presence of an electrolyte, which occurs during chemical mechanical processing (CMP) when a semiconductor wafer is wet, electrical current can flow from one metal interconnect to another and cause electrolysis. During electrolysis, a metal interconnect can be oxidized (anode) forming ions that may be transported and reduced at another metal interconnect (cathode). The metal that is reduced at the cathode may grow and form a dendrite that leads to electrical shorts between the metal interconnects. The metal that is oxidized at the anode may dissolve leading to voids and electrical opens between the metal interconnects. In either case (shorts or opens) the electrolysis causes circuits to fail and decreases reliability.
The current source needed for electrolysis to occur may arise from several phenomena including thermal or photo-generation of electron-hole pairs (ehp's) at the silicon level. In the presence of photons (e.g., lights) with energies greater than the band-gap for silicon (˜1.1 eV), ehp's may be generated and separated at p-n junctions. Under such conditions electrical potentials are favorable for electrolysis at the surface and photogeneration of ehp's acts as the current source. The amount of current is proportional to the area of the p-n junction, relative doping of the p and n regions, and the amount and location of absorbed photons. Ehp's are generated near the surface of a semiconductor wafer depending on the adsorption and extinction co-efficient of the semiconductor wafer. The amount of adsorbed radiation generally follows a Beer's law relationship, decaying exponentially with depth into the surface of the semiconductor wafer. The collection efficiency of these photons (percent of photons leading to electrical current) depends on many factors including: photon energy, dopant types, dopant concentration profiles, recombination rates and generation rates.
One solution to minimize electrolysis (i.e., dendrite formation) is to polish and scrub the semiconductor wafer in darkness to prevent carrier photo-generation such as by turning off the lights in a manufacturing room. While processing the semiconductor wafer in darkness or dim light, may reduce dendrite formation, thermal generation of carriers may allow significant corrosion to occur depending on the structure of the device and the processing environment. In addition, polishing the wafers in a dark or dim environment creates difficulties for operators and engineers to see in the manufacturing room, which increases the risk of accidents, such as dropping and breaking the semiconductor wafer or human injury.
To enable operators and engineers to see in the manufacturing room while still minimizing dendritic formation and growth, the windows of CMP tools or scrubbers can be covered with an opaque material to prevent light from reaching the semiconductor wafer when it is wet and most prone to dendrite formation. However, the opaque material on the CMP tool prevents operators and engineers from viewing the semiconductor wafer during processing to determine if, for example, the semiconductor wafer has stopped being processed or the polishing solution has stopped flowing for unknown reasons. Furthermore, if for some reason it is necessary for the semiconductor wafer to be removed (e.g., if processing stops because the semiconductor wafer is stuck in the CMP tool), once the door of the CMP tool is opened, electrolysis may occur and the semiconductor wafer may suffer reliability problems or yield loss. Therefore, a need exits to overcome the problems of the above processes while minimizing electrolysis and hence formation and growth.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.